From d3a0cc3a8ba6dfeb64d3faeffdeb6845b60e5840 Mon Sep 17 00:00:00 2001 From: Yuchen Pei Date: Sat, 20 Jan 2018 15:41:49 +0100 Subject: rearranged the dir for github - removed tools and pdfs - rearranged the projects dirs - added md files - other minor changes --- projects/05/CPU.hdl | 82 ----------------------------------------------------- 1 file changed, 82 deletions(-) delete mode 100644 projects/05/CPU.hdl (limited to 'projects/05/CPU.hdl') diff --git a/projects/05/CPU.hdl b/projects/05/CPU.hdl deleted file mode 100644 index aeeac04..0000000 --- a/projects/05/CPU.hdl +++ /dev/null @@ -1,82 +0,0 @@ -// This file is part of www.nand2tetris.org -// and the book "The Elements of Computing Systems" -// by Nisan and Schocken, MIT Press. -// File name: projects/05/CPU.hdl - -/** - * The Hack CPU (Central Processing unit), consisting of an ALU, - * two registers named A and D, and a program counter named PC. - * The CPU is designed to fetch and execute instructions written in - * the Hack machine language. In particular, functions as follows: - * Executes the inputted instruction according to the Hack machine - * language specification. The D and A in the language specification - * refer to CPU-resident registers, while M refers to the external - * memory location addressed by A, i.e. to Memory[A]. The inM input - * holds the value of this location. If the current instruction needs - * to write a value to M, the value is placed in outM, the address - * of the target location is placed in the addressM output, and the - * writeM control bit is asserted. (When writeM==0, any value may - * appear in outM). The outM and writeM outputs are combinational: - * they are affected instantaneously by the execution of the current - * instruction. The addressM and pc outputs are clocked: although they - * are affected by the execution of the current instruction, they commit - * to their new values only in the next time step. If reset==1 then the - * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather - * than to the address resulting from executing the current instruction. - */ - -CHIP CPU { - - IN inM[16], // M value input (M = contents of RAM[A]) - instruction[16], // Instruction for execution - reset; // Signals whether to re-start the current - // program (reset==1) or continue executing - // the current program (reset==0). - - OUT outM[16], // M value output - writeM, // Write to M? - addressM[15], // Address in data memory (of M) - pc[15]; // address of next instruction - - PARTS: - // Put your code here: - - Nand(a=instruction[15], b=instruction[5], out=c7); - Mux16(a=aluout, b=instruction, sel=c7, out=out1); - - Not(in=instruction[15], out=notd1); - Or(a=instruction[5], b=notd1, out=c8); - ARegister(in=out1, load=c8, out=out2, out[0..14]=addressM); - - And(a=instruction[15], b=instruction[12], out=c9); - Mux16(a=out2, b=inM, sel=c9, out=y); - - And(a=instruction[15], b=instruction[4], out=c10); - DRegister(in=aluout, load=c10, out=x); - - ALU(x=x, y=y, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=aluout, out=outM, ng=ng, zr=zr); - Not(in=ng, out=ps); - Not(in=zr, out=nz); - - And(a=ps, b=nz, out=out3); - And(a=out3, b=instruction[0], out=isjump1); - - And(a=ps, b=zr, out=out4); - And(a=out4, b=instruction[1], out=isjump2); - - And(a=ng, b=nz, out=out5); - And(a=out5, b=instruction[2], out=isjump3); - - Or(a=isjump1, b=isjump2, out=isjump4); - Or(a=isjump3, b=isjump4, out=isjump5); - And(a=instruction[15], b=isjump5, out=isjump); - - Not(in=isjump, out=isnotjump); - - PC(in=out2, load=isjump, inc=isnotjump, reset=reset, out[0..14]=pc); - - And(a=instruction[15], b=instruction[3], out=writeM); - //And(a=instruction[15], b=instruction[3], out=out6); - //DFF(in=out6, out=writeM); - -} -- cgit v1.2.3