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authorYuchen Pei <me@ypei.me>2018-01-20 15:41:49 +0100
committerYuchen Pei <me@ypei.me>2018-01-20 15:41:49 +0100
commitd3a0cc3a8ba6dfeb64d3faeffdeb6845b60e5840 (patch)
treed58df9ec2480e2a9ec6240f9c797f83d1a0b1056 /chips/RAM4K.hdl
parent3571f998b28fbc8d9250ba04c983935f10a16c15 (diff)
rearranged the dir for github
- removed tools and pdfs - rearranged the projects dirs - added md files - other minor changes
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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/b/RAM4K.hdl
+
+/**
+ * Memory of 4K registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then
+ * the in value is loaded into the memory location specified by address
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM4K {
+ IN in[16], load, address[12];
+ OUT out[16];
+
+ PARTS:
+ // Put your code here:
+ DMux8Way (in=load, sel=address[0..2], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
+ RAM512 (in=in, load=load0, address=address[3..11], out=out0);
+ RAM512 (in=in, load=load1, address=address[3..11], out=out1);
+ RAM512 (in=in, load=load2, address=address[3..11], out=out2);
+ RAM512 (in=in, load=load3, address=address[3..11], out=out3);
+ RAM512 (in=in, load=load4, address=address[3..11], out=out4);
+ RAM512 (in=in, load=load5, address=address[3..11], out=out5);
+ RAM512 (in=in, load=load6, address=address[3..11], out=out6);
+ RAM512 (in=in, load=load7, address=address[3..11], out=out7);
+ Mux8Way16 (a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[0..2], out=out);
+}