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authorYuchen Pei <me@ypei.me>2017-12-07 16:38:00 +0100
committerYuchen Pei <me@ypei.me>2017-12-07 16:38:00 +0100
commit4584283403948cc6d1bd49a83e0fca47a58f8e9f (patch)
treee5f160df9833f8a8d8e76b64476a82bb3dfea0ca /projects/03/a/RAM8.hdl
parent317270a4daf0bfa6ee1f287a3150f3f752d28391 (diff)
almost finished project 3
Diffstat (limited to 'projects/03/a/RAM8.hdl')
-rw-r--r--projects/03/a/RAM8.hdl20
1 files changed, 10 insertions, 10 deletions
diff --git a/projects/03/a/RAM8.hdl b/projects/03/a/RAM8.hdl
index 8b25522..2ea13a1 100644
--- a/projects/03/a/RAM8.hdl
+++ b/projects/03/a/RAM8.hdl
@@ -16,14 +16,14 @@ CHIP RAM8 {
PARTS:
// Put your code here:
- DMux8Way (in=load, sel=address, out=loads);
- Register (in=in, load=loads[0], out=outs[0]);
- Register (in=in, load=loads[1], out=outs[1]);
- Register (in=in, load=loads[2], out=outs[2]);
- Register (in=in, load=loads[3], out=outs[3]);
- Register (in=in, load=loads[4], out=outs[4]);
- Register (in=in, load=loads[5], out=outs[5]);
- Register (in=in, load=loads[6], out=outs[6]);
- Register (in=in, load=loads[7], out=outs[7]);
- Mux8Way(in=outs, sel=address, out=out);
+ DMux8Way (in=load, sel=address, a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
+ Register (in=in, load=load0, out=out0);
+ Register (in=in, load=load1, out=out1);
+ Register (in=in, load=load2, out=out2);
+ Register (in=in, load=load3, out=out3);
+ Register (in=in, load=load4, out=out4);
+ Register (in=in, load=load5, out=out5);
+ Register (in=in, load=load6, out=out6);
+ Register (in=in, load=load7, out=out7);
+ Mux8Way16 (a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address, out=out);
}