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authorYuchen Pei <me@ypei.me>2017-12-06 16:32:34 +0100
committerYuchen Pei <me@ypei.me>2017-12-06 16:32:34 +0100
commit317270a4daf0bfa6ee1f287a3150f3f752d28391 (patch)
tree5add14d5147aacfb41a21c144adec79cc0b61abe /projects/03/a/Register.hdl
parentd4e7065850203ff97a1046615644f9a6f73eb523 (diff)
working through project 3
- reached RAM8
Diffstat (limited to 'projects/03/a/Register.hdl')
-rw-r--r--projects/03/a/Register.hdl16
1 files changed, 16 insertions, 0 deletions
diff --git a/projects/03/a/Register.hdl b/projects/03/a/Register.hdl
index 926b99f..f4ec7ee 100644
--- a/projects/03/a/Register.hdl
+++ b/projects/03/a/Register.hdl
@@ -15,4 +15,20 @@ CHIP Register {
PARTS:
// Put your code here:
+ Bit (in=in[0], load=load, out=out[0]);
+ Bit (in=in[1], load=load, out=out[1]);
+ Bit (in=in[2], load=load, out=out[2]);
+ Bit (in=in[3], load=load, out=out[3]);
+ Bit (in=in[4], load=load, out=out[4]);
+ Bit (in=in[5], load=load, out=out[5]);
+ Bit (in=in[6], load=load, out=out[6]);
+ Bit (in=in[7], load=load, out=out[7]);
+ Bit (in=in[8], load=load, out=out[8]);
+ Bit (in=in[9], load=load, out=out[9]);
+ Bit (in=in[10], load=load, out=out[10]);
+ Bit (in=in[11], load=load, out=out[11]);
+ Bit (in=in[12], load=load, out=out[12]);
+ Bit (in=in[13], load=load, out=out[13]);
+ Bit (in=in[14], load=load, out=out[14]);
+ Bit (in=in[15], load=load, out=out[15]);
}