diff options
| author | Yuchen Pei <me@ypei.me> | 2017-12-17 09:55:39 +0100 |
|---|---|---|
| committer | Yuchen Pei <me@ypei.me> | 2017-12-17 09:55:39 +0100 |
| commit | 2e26c3ff80fe5c934a1a0a59f663c6ac45ded56a (patch) | |
| tree | 38b6984557eef5c33f9eb88697a3a0a16d1dd1ea /projects/05 | |
| parent | a564e06beb41a73fb635fac9aef4ca50bc8843b9 (diff) | |
finished CPU
Diffstat (limited to 'projects/05')
| -rw-r--r-- | projects/05/CPU.hdl | 39 | ||||
| -rw-r--r-- | projects/05/CPU.out | 93 |
2 files changed, 131 insertions, 1 deletions
diff --git a/projects/05/CPU.hdl b/projects/05/CPU.hdl index 7b73ca0..904a521 100644 --- a/projects/05/CPU.hdl +++ b/projects/05/CPU.hdl @@ -40,4 +40,41 @@ CHIP CPU { PARTS:
// Put your code here:
-}
\ No newline at end of file +
+ Nand(a=instruction[15], b=instruction[5], out=c7);
+ Mux16(a=aluout, b=instruction, sel=c7, out=out1);
+
+ Not(in=instruction[15], out=notd1);
+ Or(a=instruction[5], b=notd1, out=c8);
+ ARegister(in=out1, load=c8, out=out2, out[0..14]=addressM);
+
+ And(a=instruction[15], b=instruction[12], out=c9);
+ Mux16(a=out2, b=inM, sel=c9, out=y);
+
+ And(a=instruction[15], b=instruction[4], out=c10);
+ DRegister(in=aluout, load=c10, out=x);
+
+ ALU(x=x, y=y, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=aluout, out=outM, ng=ng, zr=zr);
+ Not(in=ng, out=ps);
+ Not(in=zr, out=nz);
+
+ And(a=ps, b=nz, out=out3);
+ And(a=out3, b=instruction[0], out=isjump1);
+
+ And(a=ps, b=zr, out=out4);
+ And(a=out4, b=instruction[1], out=isjump2);
+
+ And(a=ng, b=nz, out=out5);
+ And(a=out5, b=instruction[2], out=isjump3);
+
+ Or(a=isjump1, b=isjump2, out=isjump4);
+ Or(a=isjump3, b=isjump4, out=isjump5);
+ And(a=instruction[15], b=isjump5, out=isjump);
+
+ Not(in=isjump, out=isnotjump);
+
+ PC(in=out2, load=isjump, inc=isnotjump, reset=reset, out[0..14]=pc);
+
+ And(a=instruction[15], b=instruction[3], out=writeM);
+
+}
diff --git a/projects/05/CPU.out b/projects/05/CPU.out new file mode 100644 index 0000000..95f17b5 --- /dev/null +++ b/projects/05/CPU.out @@ -0,0 +1,93 @@ +|time| inM | instruction |reset| outM |writeM |addre| pc |DRegiste| +|0+ | 0|0011000000111001| 0 | 0| 0 | 0| 0| 0 | +|1 | 0|0011000000111001| 0 | 0| 0 |12345| 1| 0 | +|1+ | 0|1110110000010000| 0 | 12345| 0 |12345| 1| 12345 | +|2 | 0|1110110000010000| 0 | 12345| 0 |12345| 2| 12345 | +|2+ | 0|0101101110100000| 0 | -1| 0 |12345| 2| 12345 | +|3 | 0|0101101110100000| 0 | -1| 0 |23456| 3| 12345 | +|3+ | 0|1110000111010000| 0 | 11111| 0 |23456| 3| 11111 | +|4 | 0|1110000111010000| 0 | 12345| 0 |23456| 4| 11111 | +|4+ | 0|0000001111101000| 0 | -11111| 0 |23456| 4| 11111 | +|5 | 0|0000001111101000| 0 | -11111| 0 | 1000| 5| 11111 | +|5+ | 0|1110001100001000| 0 | 11111| 1 | 1000| 5| 11111 | +|6 | 0|1110001100001000| 0 | 11111| 1 | 1000| 6| 11111 | +|6+ | 0|0000001111101001| 0 | -11111| 0 | 1000| 6| 11111 | +|7 | 0|0000001111101001| 0 | -11111| 0 | 1001| 7| 11111 | +|7+ | 0|1110001110011000| 0 | 11110| 1 | 1001| 7| 11110 | +|8 | 0|1110001110011000| 0 | 11109| 1 | 1001| 8| 11110 | +|8+ | 0|0000001111101000| 0 | -11110| 0 | 1001| 8| 11110 | +|9 | 0|0000001111101000| 0 | -11110| 0 | 1000| 9| 11110 | +|9+ | 11111|1111010011010000| 0 | -1| 0 | 1000| 9| -1 | +|10 | 11111|1111010011010000| 0 | -11112| 0 | 1000| 10| -1 | +|10+ | 11111|0000000000001110| 0 | 1000| 0 | 1000| 10| -1 | +|11 | 11111|0000000000001110| 0 | 14| 0 | 14| 11| -1 | +|11+ | 11111|1110001100000100| 0 | -1| 0 | 14| 11| -1 | +|12 | 11111|1110001100000100| 0 | -1| 0 | 14| 14| -1 | +|12+ | 11111|0000001111100111| 0 | 1| 0 | 14| 14| -1 | +|13 | 11111|0000001111100111| 0 | 1| 0 | 999| 15| -1 | +|13+ | 11111|1110110111100000| 0 | 1000| 0 | 999| 15| -1 | +|14 | 11111|1110110111100000| 0 | 1001| 0 | 1000| 16| -1 | +|14+ | 11111|1110001100001000| 0 | -1| 1 | 1000| 16| -1 | +|15 | 11111|1110001100001000| 0 | -1| 1 | 1000| 17| -1 | +|15+ | 11111|0000000000010101| 0 | 1000| 0 | 1000| 17| -1 | +|16 | 11111|0000000000010101| 0 | 21| 0 | 21| 18| -1 | +|16+ | 11111|1110011111000010| 0 | 0| 0 | 21| 18| -1 | +|17 | 11111|1110011111000010| 0 | 0| 0 | 21| 21| -1 | +|17+ | 11111|0000000000000010| 0 | 21| 0 | 21| 21| -1 | +|18 | 11111|0000000000000010| 0 | 2| 0 | 2| 22| -1 | +|18+ | 11111|1110000010010000| 0 | 1| 0 | 2| 22| 1 | +|19 | 11111|1110000010010000| 0 | 3| 0 | 2| 23| 1 | +|19+ | 11111|0000001111101000| 0 | -1| 0 | 2| 23| 1 | +|20 | 11111|0000001111101000| 0 | -1| 0 | 1000| 24| 1 | +|20+ | 11111|1110111010010000| 0 | -1| 0 | 1000| 24| -1 | +|21 | 11111|1110111010010000| 0 | -1| 0 | 1000| 25| -1 | +|21+ | 11111|1110001100000001| 0 | -1| 0 | 1000| 25| -1 | +|22 | 11111|1110001100000001| 0 | -1| 0 | 1000| 26| -1 | +|22+ | 11111|1110001100000010| 0 | -1| 0 | 1000| 26| -1 | +|23 | 11111|1110001100000010| 0 | -1| 0 | 1000| 27| -1 | +|23+ | 11111|1110001100000011| 0 | -1| 0 | 1000| 27| -1 | +|24 | 11111|1110001100000011| 0 | -1| 0 | 1000| 28| -1 | +|24+ | 11111|1110001100000100| 0 | -1| 0 | 1000| 28| -1 | +|25 | 11111|1110001100000100| 0 | -1| 0 | 1000| 1000| -1 | +|25+ | 11111|1110001100000101| 0 | -1| 0 | 1000| 1000| -1 | +|26 | 11111|1110001100000101| 0 | -1| 0 | 1000| 1000| -1 | +|26+ | 11111|1110001100000110| 0 | -1| 0 | 1000| 1000| -1 | +|27 | 11111|1110001100000110| 0 | -1| 0 | 1000| 1000| -1 | +|27+ | 11111|1110001100000111| 0 | -1| 0 | 1000| 1000| -1 | +|28 | 11111|1110001100000111| 0 | -1| 0 | 1000| 1000| -1 | +|28+ | 11111|1110101010010000| 0 | 0| 0 | 1000| 1000| 0 | +|29 | 11111|1110101010010000| 0 | 0| 0 | 1000| 1001| 0 | +|29+ | 11111|1110001100000001| 0 | 0| 0 | 1000| 1001| 0 | +|30 | 11111|1110001100000001| 0 | 0| 0 | 1000| 1002| 0 | +|30+ | 11111|1110001100000010| 0 | 0| 0 | 1000| 1002| 0 | +|31 | 11111|1110001100000010| 0 | 0| 0 | 1000| 1000| 0 | +|31+ | 11111|1110001100000011| 0 | 0| 0 | 1000| 1000| 0 | +|32 | 11111|1110001100000011| 0 | 0| 0 | 1000| 1000| 0 | +|32+ | 11111|1110001100000100| 0 | 0| 0 | 1000| 1000| 0 | +|33 | 11111|1110001100000100| 0 | 0| 0 | 1000| 1001| 0 | +|33+ | 11111|1110001100000101| 0 | 0| 0 | 1000| 1001| 0 | +|34 | 11111|1110001100000101| 0 | 0| 0 | 1000| 1002| 0 | +|34+ | 11111|1110001100000110| 0 | 0| 0 | 1000| 1002| 0 | +|35 | 11111|1110001100000110| 0 | 0| 0 | 1000| 1000| 0 | +|35+ | 11111|1110001100000111| 0 | 0| 0 | 1000| 1000| 0 | +|36 | 11111|1110001100000111| 0 | 0| 0 | 1000| 1000| 0 | +|36+ | 11111|1110111111010000| 0 | 1| 0 | 1000| 1000| 1 | +|37 | 11111|1110111111010000| 0 | 1| 0 | 1000| 1001| 1 | +|37+ | 11111|1110001100000001| 0 | 1| 0 | 1000| 1001| 1 | +|38 | 11111|1110001100000001| 0 | 1| 0 | 1000| 1000| 1 | +|38+ | 11111|1110001100000010| 0 | 1| 0 | 1000| 1000| 1 | +|39 | 11111|1110001100000010| 0 | 1| 0 | 1000| 1001| 1 | +|39+ | 11111|1110001100000011| 0 | 1| 0 | 1000| 1001| 1 | +|40 | 11111|1110001100000011| 0 | 1| 0 | 1000| 1000| 1 | +|40+ | 11111|1110001100000100| 0 | 1| 0 | 1000| 1000| 1 | +|41 | 11111|1110001100000100| 0 | 1| 0 | 1000| 1001| 1 | +|41+ | 11111|1110001100000101| 0 | 1| 0 | 1000| 1001| 1 | +|42 | 11111|1110001100000101| 0 | 1| 0 | 1000| 1000| 1 | +|42+ | 11111|1110001100000110| 0 | 1| 0 | 1000| 1000| 1 | +|43 | 11111|1110001100000110| 0 | 1| 0 | 1000| 1001| 1 | +|43+ | 11111|1110001100000111| 0 | 1| 0 | 1000| 1001| 1 | +|44 | 11111|1110001100000111| 0 | 1| 0 | 1000| 1000| 1 | +|44+ | 11111|1110001100000111| 1 | 1| 0 | 1000| 1000| 1 | +|45 | 11111|1110001100000111| 1 | 1| 0 | 1000| 0| 1 | +|45+ | 11111|0111111111111111| 0 | 1| 0 | 1000| 0| 1 | +|46 | 11111|0111111111111111| 0 | 1| 0 |32767| 1| 1 | |