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-rw-r--r--projects/03/a/PC.hdl4
-rw-r--r--projects/03/a/PC.out5
-rw-r--r--projects/03/a/RAM64.hdl12
-rw-r--r--projects/03/a/RAM64.out320
-rw-r--r--projects/03/a/RAM8.hdl20
-rw-r--r--projects/03/a/RAM8.out8
-rw-r--r--projects/03/b/RAM16K.hdl8
-rw-r--r--projects/03/b/RAM16K.out320
-rw-r--r--projects/03/b/RAM4K.hdl12
-rw-r--r--projects/03/b/RAM512.hdl12
10 files changed, 707 insertions, 14 deletions
diff --git a/projects/03/a/PC.hdl b/projects/03/a/PC.hdl
index a326e43..817ff67 100644
--- a/projects/03/a/PC.hdl
+++ b/projects/03/a/PC.hdl
@@ -17,4 +17,8 @@ CHIP PC {
PARTS:
// Put your code here:
+ Register (in=in, load=load, out=regout);
+ Inc16 (in=regout, out=incout);
+ Mux16 (a=incout, b=regout, sel=load, out=regincout);
+ Mux16 (a=regout, b=false, sel=reset, out=out);
}
diff --git a/projects/03/a/PC.out b/projects/03/a/PC.out
new file mode 100644
index 0000000..8bd9bf5
--- /dev/null
+++ b/projects/03/a/PC.out
@@ -0,0 +1,5 @@
+| time | in |reset|load | inc | out |
+| 0+ | 0 | 0 | 0 | 0 | 0 |
+| 1 | 0 | 0 | 0 | 0 | 0 |
+| 1+ | 0 | 0 | 0 | 1 | 0 |
+| 2 | 0 | 0 | 0 | 1 | 0 |
diff --git a/projects/03/a/RAM64.hdl b/projects/03/a/RAM64.hdl
index 66efcbd..269adb1 100644
--- a/projects/03/a/RAM64.hdl
+++ b/projects/03/a/RAM64.hdl
@@ -16,4 +16,14 @@ CHIP RAM64 {
PARTS:
// Put your code here:
-} \ No newline at end of file
+ DMux8Way (in=load, sel=address[0..2], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
+ RAM8 (in=in, load=load0, address=address[3..5], out=out0);
+ RAM8 (in=in, load=load1, address=address[3..5], out=out1);
+ RAM8 (in=in, load=load2, address=address[3..5], out=out2);
+ RAM8 (in=in, load=load3, address=address[3..5], out=out3);
+ RAM8 (in=in, load=load4, address=address[3..5], out=out4);
+ RAM8 (in=in, load=load5, address=address[3..5], out=out5);
+ RAM8 (in=in, load=load6, address=address[3..5], out=out6);
+ RAM8 (in=in, load=load7, address=address[3..5], out=out7);
+ Mux8Way16 (a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[0..2], out=out);
+}
diff --git a/projects/03/a/RAM64.out b/projects/03/a/RAM64.out
new file mode 100644
index 0000000..554ce39
--- /dev/null
+++ b/projects/03/a/RAM64.out
@@ -0,0 +1,320 @@
+| time | in |load |address| out |
+| 0+ | 0 | 0 | 0 | 0 |
+| 1 | 0 | 0 | 0 | 0 |
+| 1+ | 0 | 1 | 0 | 0 |
+| 2 | 0 | 1 | 0 | 0 |
+| 2+ | 1313 | 0 | 0 | 0 |
+| 3 | 1313 | 0 | 0 | 0 |
+| 3+ | 1313 | 1 | 13 | 0 |
+| 4 | 1313 | 1 | 13 | 1313 |
+| 4+ | 1313 | 0 | 0 | 0 |
+| 5 | 1313 | 0 | 0 | 0 |
+| 5+ | 4747 | 0 | 47 | 0 |
+| 6 | 4747 | 0 | 47 | 0 |
+| 6+ | 4747 | 1 | 47 | 0 |
+| 7 | 4747 | 1 | 47 | 4747 |
+| 7+ | 4747 | 0 | 47 | 4747 |
+| 8 | 4747 | 0 | 47 | 4747 |
+| 8 | 4747 | 0 | 13 | 1313 |
+| 8+ | 6363 | 0 | 13 | 1313 |
+| 9 | 6363 | 0 | 13 | 1313 |
+| 9+ | 6363 | 1 | 63 | 0 |
+| 10 | 6363 | 1 | 63 | 6363 |
+| 10+ | 6363 | 0 | 63 | 6363 |
+| 11 | 6363 | 0 | 63 | 6363 |
+| 11 | 6363 | 0 | 47 | 4747 |
+| 11 | 6363 | 0 | 63 | 6363 |
+| 11+ | 6363 | 0 | 40 | 0 |
+| 12 | 6363 | 0 | 40 | 0 |
+| 12 | 6363 | 0 | 41 | 0 |
+| 12 | 6363 | 0 | 42 | 0 |
+| 12 | 6363 | 0 | 43 | 0 |
+| 12 | 6363 | 0 | 44 | 0 |
+| 12 | 6363 | 0 | 45 | 0 |
+| 12 | 6363 | 0 | 46 | 0 |
+| 12 | 6363 | 0 | 47 | 4747 |
+| 12+ | 21845 | 1 | 40 | 0 |
+| 13 | 21845 | 1 | 40 | 21845 |
+| 13+ | 21845 | 1 | 41 | 0 |
+| 14 | 21845 | 1 | 41 | 21845 |
+| 14+ | 21845 | 1 | 42 | 0 |
+| 15 | 21845 | 1 | 42 | 21845 |
+| 15+ | 21845 | 1 | 43 | 0 |
+| 16 | 21845 | 1 | 43 | 21845 |
+| 16+ | 21845 | 1 | 44 | 0 |
+| 17 | 21845 | 1 | 44 | 21845 |
+| 17+ | 21845 | 1 | 45 | 0 |
+| 18 | 21845 | 1 | 45 | 21845 |
+| 18+ | 21845 | 1 | 46 | 0 |
+| 19 | 21845 | 1 | 46 | 21845 |
+| 19+ | 21845 | 1 | 47 | 4747 |
+| 20 | 21845 | 1 | 47 | 21845 |
+| 20+ | 21845 | 0 | 40 | 21845 |
+| 21 | 21845 | 0 | 40 | 21845 |
+| 21 | 21845 | 0 | 41 | 21845 |
+| 21 | 21845 | 0 | 42 | 21845 |
+| 21 | 21845 | 0 | 43 | 21845 |
+| 21 | 21845 | 0 | 44 | 21845 |
+| 21 | 21845 | 0 | 45 | 21845 |
+| 21 | 21845 | 0 | 46 | 21845 |
+| 21 | 21845 | 0 | 47 | 21845 |
+| 21+ | -21846 | 1 | 40 | 21845 |
+| 22 | -21846 | 1 | 40 | -21846 |
+| 22+ | -21846 | 0 | 40 | -21846 |
+| 23 | -21846 | 0 | 40 | -21846 |
+| 23 | -21846 | 0 | 41 | 21845 |
+| 23 | -21846 | 0 | 42 | 21845 |
+| 23 | -21846 | 0 | 43 | 21845 |
+| 23 | -21846 | 0 | 44 | 21845 |
+| 23 | -21846 | 0 | 45 | 21845 |
+| 23 | -21846 | 0 | 46 | 21845 |
+| 23 | -21846 | 0 | 47 | 21845 |
+| 23+ | 21845 | 1 | 40 | -21846 |
+| 24 | 21845 | 1 | 40 | 21845 |
+| 24+ | -21846 | 1 | 41 | 21845 |
+| 25 | -21846 | 1 | 41 | -21846 |
+| 25+ | -21846 | 0 | 40 | 21845 |
+| 26 | -21846 | 0 | 40 | 21845 |
+| 26 | -21846 | 0 | 41 | -21846 |
+| 26 | -21846 | 0 | 42 | 21845 |
+| 26 | -21846 | 0 | 43 | 21845 |
+| 26 | -21846 | 0 | 44 | 21845 |
+| 26 | -21846 | 0 | 45 | 21845 |
+| 26 | -21846 | 0 | 46 | 21845 |
+| 26 | -21846 | 0 | 47 | 21845 |
+| 26+ | 21845 | 1 | 41 | -21846 |
+| 27 | 21845 | 1 | 41 | 21845 |
+| 27+ | -21846 | 1 | 42 | 21845 |
+| 28 | -21846 | 1 | 42 | -21846 |
+| 28+ | -21846 | 0 | 40 | 21845 |
+| 29 | -21846 | 0 | 40 | 21845 |
+| 29 | -21846 | 0 | 41 | 21845 |
+| 29 | -21846 | 0 | 42 | -21846 |
+| 29 | -21846 | 0 | 43 | 21845 |
+| 29 | -21846 | 0 | 44 | 21845 |
+| 29 | -21846 | 0 | 45 | 21845 |
+| 29 | -21846 | 0 | 46 | 21845 |
+| 29 | -21846 | 0 | 47 | 21845 |
+| 29+ | 21845 | 1 | 42 | -21846 |
+| 30 | 21845 | 1 | 42 | 21845 |
+| 30+ | -21846 | 1 | 43 | 21845 |
+| 31 | -21846 | 1 | 43 | -21846 |
+| 31+ | -21846 | 0 | 40 | 21845 |
+| 32 | -21846 | 0 | 40 | 21845 |
+| 32 | -21846 | 0 | 41 | 21845 |
+| 32 | -21846 | 0 | 42 | 21845 |
+| 32 | -21846 | 0 | 43 | -21846 |
+| 32 | -21846 | 0 | 44 | 21845 |
+| 32 | -21846 | 0 | 45 | 21845 |
+| 32 | -21846 | 0 | 46 | 21845 |
+| 32 | -21846 | 0 | 47 | 21845 |
+| 32+ | 21845 | 1 | 43 | -21846 |
+| 33 | 21845 | 1 | 43 | 21845 |
+| 33+ | -21846 | 1 | 44 | 21845 |
+| 34 | -21846 | 1 | 44 | -21846 |
+| 34+ | -21846 | 0 | 40 | 21845 |
+| 35 | -21846 | 0 | 40 | 21845 |
+| 35 | -21846 | 0 | 41 | 21845 |
+| 35 | -21846 | 0 | 42 | 21845 |
+| 35 | -21846 | 0 | 43 | 21845 |
+| 35 | -21846 | 0 | 44 | -21846 |
+| 35 | -21846 | 0 | 45 | 21845 |
+| 35 | -21846 | 0 | 46 | 21845 |
+| 35 | -21846 | 0 | 47 | 21845 |
+| 35+ | 21845 | 1 | 44 | -21846 |
+| 36 | 21845 | 1 | 44 | 21845 |
+| 36+ | -21846 | 1 | 45 | 21845 |
+| 37 | -21846 | 1 | 45 | -21846 |
+| 37+ | -21846 | 0 | 40 | 21845 |
+| 38 | -21846 | 0 | 40 | 21845 |
+| 38 | -21846 | 0 | 41 | 21845 |
+| 38 | -21846 | 0 | 42 | 21845 |
+| 38 | -21846 | 0 | 43 | 21845 |
+| 38 | -21846 | 0 | 44 | 21845 |
+| 38 | -21846 | 0 | 45 | -21846 |
+| 38 | -21846 | 0 | 46 | 21845 |
+| 38 | -21846 | 0 | 47 | 21845 |
+| 38+ | 21845 | 1 | 45 | -21846 |
+| 39 | 21845 | 1 | 45 | 21845 |
+| 39+ | -21846 | 1 | 46 | 21845 |
+| 40 | -21846 | 1 | 46 | -21846 |
+| 40+ | -21846 | 0 | 40 | 21845 |
+| 41 | -21846 | 0 | 40 | 21845 |
+| 41 | -21846 | 0 | 41 | 21845 |
+| 41 | -21846 | 0 | 42 | 21845 |
+| 41 | -21846 | 0 | 43 | 21845 |
+| 41 | -21846 | 0 | 44 | 21845 |
+| 41 | -21846 | 0 | 45 | 21845 |
+| 41 | -21846 | 0 | 46 | -21846 |
+| 41 | -21846 | 0 | 47 | 21845 |
+| 41+ | 21845 | 1 | 46 | -21846 |
+| 42 | 21845 | 1 | 46 | 21845 |
+| 42+ | -21846 | 1 | 47 | 21845 |
+| 43 | -21846 | 1 | 47 | -21846 |
+| 43+ | -21846 | 0 | 40 | 21845 |
+| 44 | -21846 | 0 | 40 | 21845 |
+| 44 | -21846 | 0 | 41 | 21845 |
+| 44 | -21846 | 0 | 42 | 21845 |
+| 44 | -21846 | 0 | 43 | 21845 |
+| 44 | -21846 | 0 | 44 | 21845 |
+| 44 | -21846 | 0 | 45 | 21845 |
+| 44 | -21846 | 0 | 46 | 21845 |
+| 44 | -21846 | 0 | 47 | -21846 |
+| 44+ | 21845 | 1 | 47 | -21846 |
+| 45 | 21845 | 1 | 47 | 21845 |
+| 45+ | 21845 | 0 | 40 | 21845 |
+| 46 | 21845 | 0 | 40 | 21845 |
+| 46 | 21845 | 0 | 41 | 21845 |
+| 46 | 21845 | 0 | 42 | 21845 |
+| 46 | 21845 | 0 | 43 | 21845 |
+| 46 | 21845 | 0 | 44 | 21845 |
+| 46 | 21845 | 0 | 45 | 21845 |
+| 46 | 21845 | 0 | 46 | 21845 |
+| 46 | 21845 | 0 | 47 | 21845 |
+| 46+ | 21845 | 0 | 5 | 0 |
+| 47 | 21845 | 0 | 5 | 0 |
+| 47 | 21845 | 0 | 13 | 1313 |
+| 47 | 21845 | 0 | 21 | 0 |
+| 47 | 21845 | 0 | 29 | 0 |
+| 47 | 21845 | 0 | 37 | 0 |
+| 47 | 21845 | 0 | 45 | 21845 |
+| 47 | 21845 | 0 | 53 | 0 |
+| 47 | 21845 | 0 | 61 | 0 |
+| 47+ | 21845 | 1 | 5 | 0 |
+| 48 | 21845 | 1 | 5 | 21845 |
+| 48+ | 21845 | 1 | 13 | 1313 |
+| 49 | 21845 | 1 | 13 | 21845 |
+| 49+ | 21845 | 1 | 21 | 0 |
+| 50 | 21845 | 1 | 21 | 21845 |
+| 50+ | 21845 | 1 | 29 | 0 |
+| 51 | 21845 | 1 | 29 | 21845 |
+| 51+ | 21845 | 1 | 37 | 0 |
+| 52 | 21845 | 1 | 37 | 21845 |
+| 52+ | 21845 | 1 | 45 | 21845 |
+| 53 | 21845 | 1 | 45 | 21845 |
+| 53+ | 21845 | 1 | 53 | 0 |
+| 54 | 21845 | 1 | 53 | 21845 |
+| 54+ | 21845 | 1 | 61 | 0 |
+| 55 | 21845 | 1 | 61 | 21845 |
+| 55+ | 21845 | 0 | 5 | 21845 |
+| 56 | 21845 | 0 | 5 | 21845 |
+| 56 | 21845 | 0 | 13 | 21845 |
+| 56 | 21845 | 0 | 21 | 21845 |
+| 56 | 21845 | 0 | 29 | 21845 |
+| 56 | 21845 | 0 | 37 | 21845 |
+| 56 | 21845 | 0 | 45 | 21845 |
+| 56 | 21845 | 0 | 53 | 21845 |
+| 56 | 21845 | 0 | 61 | 21845 |
+| 56+ | -21846 | 1 | 5 | 21845 |
+| 57 | -21846 | 1 | 5 | -21846 |
+| 57+ | -21846 | 0 | 5 | -21846 |
+| 58 | -21846 | 0 | 5 | -21846 |
+| 58 | -21846 | 0 | 13 | 21845 |
+| 58 | -21846 | 0 | 21 | 21845 |
+| 58 | -21846 | 0 | 29 | 21845 |
+| 58 | -21846 | 0 | 37 | 21845 |
+| 58 | -21846 | 0 | 45 | 21845 |
+| 58 | -21846 | 0 | 53 | 21845 |
+| 58 | -21846 | 0 | 61 | 21845 |
+| 58+ | 21845 | 1 | 5 | -21846 |
+| 59 | 21845 | 1 | 5 | 21845 |
+| 59+ | -21846 | 1 | 13 | 21845 |
+| 60 | -21846 | 1 | 13 | -21846 |
+| 60+ | -21846 | 0 | 5 | 21845 |
+| 61 | -21846 | 0 | 5 | 21845 |
+| 61 | -21846 | 0 | 13 | -21846 |
+| 61 | -21846 | 0 | 21 | 21845 |
+| 61 | -21846 | 0 | 29 | 21845 |
+| 61 | -21846 | 0 | 37 | 21845 |
+| 61 | -21846 | 0 | 45 | 21845 |
+| 61 | -21846 | 0 | 53 | 21845 |
+| 61 | -21846 | 0 | 61 | 21845 |
+| 61+ | 21845 | 1 | 13 | -21846 |
+| 62 | 21845 | 1 | 13 | 21845 |
+| 62+ | -21846 | 1 | 21 | 21845 |
+| 63 | -21846 | 1 | 21 | -21846 |
+| 63+ | -21846 | 0 | 5 | 21845 |
+| 64 | -21846 | 0 | 5 | 21845 |
+| 64 | -21846 | 0 | 13 | 21845 |
+| 64 | -21846 | 0 | 21 | -21846 |
+| 64 | -21846 | 0 | 29 | 21845 |
+| 64 | -21846 | 0 | 37 | 21845 |
+| 64 | -21846 | 0 | 45 | 21845 |
+| 64 | -21846 | 0 | 53 | 21845 |
+| 64 | -21846 | 0 | 61 | 21845 |
+| 64+ | 21845 | 1 | 21 | -21846 |
+| 65 | 21845 | 1 | 21 | 21845 |
+| 65+ | -21846 | 1 | 29 | 21845 |
+| 66 | -21846 | 1 | 29 | -21846 |
+| 66+ | -21846 | 0 | 5 | 21845 |
+| 67 | -21846 | 0 | 5 | 21845 |
+| 67 | -21846 | 0 | 13 | 21845 |
+| 67 | -21846 | 0 | 21 | 21845 |
+| 67 | -21846 | 0 | 29 | -21846 |
+| 67 | -21846 | 0 | 37 | 21845 |
+| 67 | -21846 | 0 | 45 | 21845 |
+| 67 | -21846 | 0 | 53 | 21845 |
+| 67 | -21846 | 0 | 61 | 21845 |
+| 67+ | 21845 | 1 | 29 | -21846 |
+| 68 | 21845 | 1 | 29 | 21845 |
+| 68+ | -21846 | 1 | 37 | 21845 |
+| 69 | -21846 | 1 | 37 | -21846 |
+| 69+ | -21846 | 0 | 5 | 21845 |
+| 70 | -21846 | 0 | 5 | 21845 |
+| 70 | -21846 | 0 | 13 | 21845 |
+| 70 | -21846 | 0 | 21 | 21845 |
+| 70 | -21846 | 0 | 29 | 21845 |
+| 70 | -21846 | 0 | 37 | -21846 |
+| 70 | -21846 | 0 | 45 | 21845 |
+| 70 | -21846 | 0 | 53 | 21845 |
+| 70 | -21846 | 0 | 61 | 21845 |
+| 70+ | 21845 | 1 | 37 | -21846 |
+| 71 | 21845 | 1 | 37 | 21845 |
+| 71+ | -21846 | 1 | 45 | 21845 |
+| 72 | -21846 | 1 | 45 | -21846 |
+| 72+ | -21846 | 0 | 5 | 21845 |
+| 73 | -21846 | 0 | 5 | 21845 |
+| 73 | -21846 | 0 | 13 | 21845 |
+| 73 | -21846 | 0 | 21 | 21845 |
+| 73 | -21846 | 0 | 29 | 21845 |
+| 73 | -21846 | 0 | 37 | 21845 |
+| 73 | -21846 | 0 | 45 | -21846 |
+| 73 | -21846 | 0 | 53 | 21845 |
+| 73 | -21846 | 0 | 61 | 21845 |
+| 73+ | 21845 | 1 | 45 | -21846 |
+| 74 | 21845 | 1 | 45 | 21845 |
+| 74+ | -21846 | 1 | 53 | 21845 |
+| 75 | -21846 | 1 | 53 | -21846 |
+| 75+ | -21846 | 0 | 5 | 21845 |
+| 76 | -21846 | 0 | 5 | 21845 |
+| 76 | -21846 | 0 | 13 | 21845 |
+| 76 | -21846 | 0 | 21 | 21845 |
+| 76 | -21846 | 0 | 29 | 21845 |
+| 76 | -21846 | 0 | 37 | 21845 |
+| 76 | -21846 | 0 | 45 | 21845 |
+| 76 | -21846 | 0 | 53 | -21846 |
+| 76 | -21846 | 0 | 61 | 21845 |
+| 76+ | 21845 | 1 | 53 | -21846 |
+| 77 | 21845 | 1 | 53 | 21845 |
+| 77+ | -21846 | 1 | 61 | 21845 |
+| 78 | -21846 | 1 | 61 | -21846 |
+| 78+ | -21846 | 0 | 5 | 21845 |
+| 79 | -21846 | 0 | 5 | 21845 |
+| 79 | -21846 | 0 | 13 | 21845 |
+| 79 | -21846 | 0 | 21 | 21845 |
+| 79 | -21846 | 0 | 29 | 21845 |
+| 79 | -21846 | 0 | 37 | 21845 |
+| 79 | -21846 | 0 | 45 | 21845 |
+| 79 | -21846 | 0 | 53 | 21845 |
+| 79 | -21846 | 0 | 61 | -21846 |
+| 79+ | 21845 | 1 | 61 | -21846 |
+| 80 | 21845 | 1 | 61 | 21845 |
+| 80+ | 21845 | 0 | 5 | 21845 |
+| 81 | 21845 | 0 | 5 | 21845 |
+| 81 | 21845 | 0 | 13 | 21845 |
+| 81 | 21845 | 0 | 21 | 21845 |
+| 81 | 21845 | 0 | 29 | 21845 |
+| 81 | 21845 | 0 | 37 | 21845 |
+| 81 | 21845 | 0 | 45 | 21845 |
+| 81 | 21845 | 0 | 53 | 21845 |
+| 81 | 21845 | 0 | 61 | 21845 |
diff --git a/projects/03/a/RAM8.hdl b/projects/03/a/RAM8.hdl
index 8b25522..2ea13a1 100644
--- a/projects/03/a/RAM8.hdl
+++ b/projects/03/a/RAM8.hdl
@@ -16,14 +16,14 @@ CHIP RAM8 {
PARTS:
// Put your code here:
- DMux8Way (in=load, sel=address, out=loads);
- Register (in=in, load=loads[0], out=outs[0]);
- Register (in=in, load=loads[1], out=outs[1]);
- Register (in=in, load=loads[2], out=outs[2]);
- Register (in=in, load=loads[3], out=outs[3]);
- Register (in=in, load=loads[4], out=outs[4]);
- Register (in=in, load=loads[5], out=outs[5]);
- Register (in=in, load=loads[6], out=outs[6]);
- Register (in=in, load=loads[7], out=outs[7]);
- Mux8Way(in=outs, sel=address, out=out);
+ DMux8Way (in=load, sel=address, a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
+ Register (in=in, load=load0, out=out0);
+ Register (in=in, load=load1, out=out1);
+ Register (in=in, load=load2, out=out2);
+ Register (in=in, load=load3, out=out3);
+ Register (in=in, load=load4, out=out4);
+ Register (in=in, load=load5, out=out5);
+ Register (in=in, load=load6, out=out6);
+ Register (in=in, load=load7, out=out7);
+ Mux8Way16 (a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address, out=out);
}
diff --git a/projects/03/a/RAM8.out b/projects/03/a/RAM8.out
new file mode 100644
index 0000000..9499c03
--- /dev/null
+++ b/projects/03/a/RAM8.out
@@ -0,0 +1,8 @@
+| time | in |load |address| out |
+| 0+ | 0 | 0 | 0 | 0 |
+| 1 | 0 | 0 | 0 | 0 |
+| 1+ | 0 | 1 | 0 | 0 |
+| 2 | 0 | 1 | 0 | 0 |
+| 2+ | 11111 | 0 | 0 | 0 |
+| 3 | 11111 | 0 | 0 | 0 |
+| 3+ | 11111 | 1 | 1 | 0 |
diff --git a/projects/03/b/RAM16K.hdl b/projects/03/b/RAM16K.hdl
index 119a19e..9c6e89f 100644
--- a/projects/03/b/RAM16K.hdl
+++ b/projects/03/b/RAM16K.hdl
@@ -16,4 +16,10 @@ CHIP RAM16K {
PARTS:
// Put your code here:
-} \ No newline at end of file
+ DMux4Way (in=load, sel=address[0..1], a=load0, b=load1, c=load2, d=load3);
+ RAM4K (in=in, load=load0, address=address[2..13], out=out0);
+ RAM4K (in=in, load=load1, address=address[2..13], out=out1);
+ RAM4K (in=in, load=load2, address=address[2..13], out=out2);
+ RAM4K (in=in, load=load3, address=address[2..13], out=out3);
+ Mux4Way16 (a=out0, b=out1, c=out2, d=out3, sel=address[0..1], out=out);
+}
diff --git a/projects/03/b/RAM16K.out b/projects/03/b/RAM16K.out
new file mode 100644
index 0000000..2caabe9
--- /dev/null
+++ b/projects/03/b/RAM16K.out
@@ -0,0 +1,320 @@
+| time | in |load | address | out |
+| 0+ | 0 | 0 | 0 | 0 |
+| 1 | 0 | 0 | 0 | 0 |
+| 1+ | 0 | 1 | 0 | 0 |
+| 2 | 0 | 1 | 0 | 0 |
+| 2+ | 4321 | 0 | 0 | 0 |
+| 3 | 4321 | 0 | 0 | 0 |
+| 3+ | 4321 | 1 | 4321 | 0 |
+| 4 | 4321 | 1 | 4321 | 4321 |
+| 4+ | 4321 | 0 | 0 | 0 |
+| 5 | 4321 | 0 | 0 | 0 |
+| 5+ | 12345 | 0 | 12345 | 0 |
+| 6 | 12345 | 0 | 12345 | 0 |
+| 6+ | 12345 | 1 | 12345 | 0 |
+| 7 | 12345 | 1 | 12345 | 12345 |
+| 7+ | 12345 | 0 | 12345 | 12345 |
+| 8 | 12345 | 0 | 12345 | 12345 |
+| 8 | 12345 | 0 | 4321 | 4321 |
+| 8+ | 16383 | 0 | 4321 | 4321 |
+| 9 | 16383 | 0 | 4321 | 4321 |
+| 9+ | 16383 | 1 | 16383 | 0 |
+| 10 | 16383 | 1 | 16383 | 16383 |
+| 10+ | 16383 | 0 | 16383 | 16383 |
+| 11 | 16383 | 0 | 16383 | 16383 |
+| 11 | 16383 | 0 | 12345 | 12345 |
+| 11 | 16383 | 0 | 16383 | 16383 |
+| 11+ | 16383 | 0 | 10920 | 0 |
+| 12 | 16383 | 0 | 10920 | 0 |
+| 12 | 16383 | 0 | 10921 | 0 |
+| 12 | 16383 | 0 | 10922 | 0 |
+| 12 | 16383 | 0 | 10923 | 0 |
+| 12 | 16383 | 0 | 10924 | 0 |
+| 12 | 16383 | 0 | 10925 | 0 |
+| 12 | 16383 | 0 | 10926 | 0 |
+| 12 | 16383 | 0 | 10927 | 0 |
+| 12+ | 21845 | 1 | 10920 | 0 |
+| 13 | 21845 | 1 | 10920 | 21845 |
+| 13+ | 21845 | 1 | 10921 | 0 |
+| 14 | 21845 | 1 | 10921 | 21845 |
+| 14+ | 21845 | 1 | 10922 | 0 |
+| 15 | 21845 | 1 | 10922 | 21845 |
+| 15+ | 21845 | 1 | 10923 | 0 |
+| 16 | 21845 | 1 | 10923 | 21845 |
+| 16+ | 21845 | 1 | 10924 | 0 |
+| 17 | 21845 | 1 | 10924 | 21845 |
+| 17+ | 21845 | 1 | 10925 | 0 |
+| 18 | 21845 | 1 | 10925 | 21845 |
+| 18+ | 21845 | 1 | 10926 | 0 |
+| 19 | 21845 | 1 | 10926 | 21845 |
+| 19+ | 21845 | 1 | 10927 | 0 |
+| 20 | 21845 | 1 | 10927 | 21845 |
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diff --git a/projects/03/b/RAM4K.hdl b/projects/03/b/RAM4K.hdl
index 1cee633..cfc2e4f 100644
--- a/projects/03/b/RAM4K.hdl
+++ b/projects/03/b/RAM4K.hdl
@@ -16,4 +16,14 @@ CHIP RAM4K {
PARTS:
// Put your code here:
-} \ No newline at end of file
+ DMux8Way (in=load, sel=address[0..2], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
+ RAM512 (in=in, load=load0, address=address[3..11], out=out0);
+ RAM512 (in=in, load=load1, address=address[3..11], out=out1);
+ RAM512 (in=in, load=load2, address=address[3..11], out=out2);
+ RAM512 (in=in, load=load3, address=address[3..11], out=out3);
+ RAM512 (in=in, load=load4, address=address[3..11], out=out4);
+ RAM512 (in=in, load=load5, address=address[3..11], out=out5);
+ RAM512 (in=in, load=load6, address=address[3..11], out=out6);
+ RAM512 (in=in, load=load7, address=address[3..11], out=out7);
+ Mux8Way16 (a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[0..2], out=out);
+}
diff --git a/projects/03/b/RAM512.hdl b/projects/03/b/RAM512.hdl
index 6c40f28..55f6ea0 100644
--- a/projects/03/b/RAM512.hdl
+++ b/projects/03/b/RAM512.hdl
@@ -16,4 +16,14 @@ CHIP RAM512 {
PARTS:
// Put your code here:
-} \ No newline at end of file
+ DMux8Way (in=load, sel=address[0..2], a=load0, b=load1, c=load2, d=load3, e=load4, f=load5, g=load6, h=load7);
+ RAM64 (in=in, load=load0, address=address[3..8], out=out0);
+ RAM64 (in=in, load=load1, address=address[3..8], out=out1);
+ RAM64 (in=in, load=load2, address=address[3..8], out=out2);
+ RAM64 (in=in, load=load3, address=address[3..8], out=out3);
+ RAM64 (in=in, load=load4, address=address[3..8], out=out4);
+ RAM64 (in=in, load=load5, address=address[3..8], out=out5);
+ RAM64 (in=in, load=load6, address=address[3..8], out=out6);
+ RAM64 (in=in, load=load7, address=address[3..8], out=out7);
+ Mux8Way16 (a=out0, b=out1, c=out2, d=out3, e=out4, f=out5, g=out6, h=out7, sel=address[0..2], out=out);
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 02:42:40 +0000