diff options
author | Yuchen Pei <me@ypei.me> | 2017-12-07 16:38:00 +0100 |
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committer | Yuchen Pei <me@ypei.me> | 2017-12-07 16:38:00 +0100 |
commit | 4584283403948cc6d1bd49a83e0fca47a58f8e9f (patch) | |
tree | e5f160df9833f8a8d8e76b64476a82bb3dfea0ca /projects/03/b/RAM16K.hdl | |
parent | 317270a4daf0bfa6ee1f287a3150f3f752d28391 (diff) |
almost finished project 3
Diffstat (limited to 'projects/03/b/RAM16K.hdl')
-rw-r--r-- | projects/03/b/RAM16K.hdl | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/projects/03/b/RAM16K.hdl b/projects/03/b/RAM16K.hdl index 119a19e..9c6e89f 100644 --- a/projects/03/b/RAM16K.hdl +++ b/projects/03/b/RAM16K.hdl @@ -16,4 +16,10 @@ CHIP RAM16K { PARTS:
// Put your code here:
-}
\ No newline at end of file + DMux4Way (in=load, sel=address[0..1], a=load0, b=load1, c=load2, d=load3);
+ RAM4K (in=in, load=load0, address=address[2..13], out=out0);
+ RAM4K (in=in, load=load1, address=address[2..13], out=out1);
+ RAM4K (in=in, load=load2, address=address[2..13], out=out2);
+ RAM4K (in=in, load=load3, address=address[2..13], out=out3);
+ Mux4Way16 (a=out0, b=out1, c=out2, d=out3, sel=address[0..1], out=out);
+}
|